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rev . p r b s e p t 2 0 0 1 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o . box 9106, norwood, ma 02062 - 9106 u . s . a . t e l : 7 8 1 / 3 2 9 - 4 7 0 0 w w w . a n a l o g . c o m fax: 781/326 - 8703 ?analog devices, inc., 2001 a multi - rate to 2.7gbps clock and data recovery ic with limiting amplifier preliminary technical data adn2809 features meets sonet requirements for jitter transfer / generation / tolerance q uantizer sensitivity: 6 mv typical adjustable slice leve l: +/ - 100 mv 1 .9ghz minimum bandwidth l oss of signal detect range: 4mv to 17mv si ngle reference clock frequency for all rates including 15/14 (7%) wrapper rate choice of 19.44, 38.88, 77.76 or 155.52mhz lvpecl / lvds / lvcmos / lvttl compatible inp uts ( l v pecl / lvds only at 155.52 mhz) 19.44mhz crystal oscillator for module apps l oss of lock indicator l oopback mode for high speed test data output squelch & clock recovery functions single supply operation: 3.3 volts ( + 10%) low power: 780 mw typical p atented clock recovery architecture 7 x 7 mm 48 pin lfcsp applications sonet oc - 3/12/48, sdh stm - 1/4/16, and all associated fec rates wdm transponders sonet/sdh regenerators and test equipment backplane applications product description the adn2809 provides the receiver functions of quantization, signal level detect and clock and data recovery at rates of oc - 3, oc - 12, gigabit ethernet, oc - 48 and all fec rates. all sonet jitter requirements are met, including: jitter transfer; jitter generation; and j itter tolerance. all specifications are quoted for - 40 to 85c ambient temperature unless otherwise noted. the device is intended for wdm system applications and can be used with either an external reference clock or an on - chip oscillator crystal. both na tive rates and 15/14 rate digital ?wrappers? rates are supported by the adn2809, without any change of reference clock required. this device together with a pin diode and a tia preamplifier can implement a highly integrated, low cost, low power fiber opti c receiver. the receiver front end signal detect circuit indicates when the input signal level has fallen below a user adjustable threshold. the adn2809 is available in a compact 48 pin chip scale package. functional block diagram cf loss of lock
a d n 2 8 0 9 r e v . p rb oc t . .20 0 1 - 2 - adn2809 electrical characteristics at t a =t min to t max , v cc =v min to v max , v ee =0v, c f =4.7 m f, 20 ohm esr for xo unless otherwise noted parameter conditions min typ max units quantizer ? dc characteristics input voltage range input common mod e voltage input peak - to- peak differential voltage input sensitivity, v sense (peak-to - peak differential) input overdrive, v od input maximum offset voltage input current input rms noise single ended, dc coupled @ p in or n in ? @ p in or n in ac coupled i/p 1 p in - n in , figure 2, ber= < 1 x 10 - 10 figure 3, ber = < 1 x 10 - 10 slicep, slicen = vcc ber = < 1 x 10 - 10 0 0.4 10 5 2.4 6 3 0.5 10 244 1.2 1.2 v v v mv mv mv m a m vrms quantizer - ac characteristics upper ? 3 db bandwidth small signal gain s11 maximum @ 2.5ghz, figure 7 input resistance input capacitance pulse width distortion differential single - ended 1.9 54 - 15 50 0.65 10 ghz db db w pf ps quantizer slice adjustment gain (threshold/vin) control voltage range control voltage range slice threshold offset vin = slicep - slicen slicep - slicen slicep or slicen full input range 0.131 - 0.8 1.3 - 1.0 0.134 0.8 vcc 1.0 v/v v v mv level detect level detect range (see figure 4) response time hysterises (electrical), ac coupled signal sdout output logic high sdout output logic low level detect output is a logic ?1? lvcmos c ompatible with no signal present. r thresh = 0 w r thresh = 10k w r thresh = 200k w dc coupled r thresh = 0 w r thresh = 10k w r thresh = 200k w load = +2ma ( adn2812 sources i) load = - 2ma ( adn2812 sinks i) 2 6 15 0.1 2.7 3 8.8 17 3 5 5 5 3 0.2 4 12 21 5 7 7 7 0.4 mv mv mv m s db db db v v power supply voltage v min to v max 3.0 3.6 v power supply current v min to v max 140 236 380 ma phase - locked loop characteristics jitter transfer bandwidth (see figure 5 and table 1) jitter tolerance tracking bandwidth (see figure 5 and table 1) jitter tolerance (oc -48) jitter generation (12khz to 20mhz) (12khz to 10mhz) (12khz to 5mhz) (12khz to 1.3mhz) note: sonet specs appear in bold oc- 48 gigabit ethernet oc- 12 oc- 3 oc- 48 gigabit ethernet oc- 12 oc- 3 600 hz 6 khz 100 mhz 1 mhz oc- 48 gigabit ethernet oc- 12 oc- 3 1.0 0.5 0.25 0.065 370 185 93 23 4.8 4.8 4.8 4.8 80 >20 2 5.5 >0.6 2 0.003 0.03 0.003 0.03 0.003 0.03 0.003 0.03 2000 1000 500 130 0.01 0.1 0.01 0.1 0.01 0.1 0.01 0.1 k hz k hz k hz k h z mhz mhz mhz mhz uip - p uip - p uip - p uip - p ui rms uip - p ui rms uip - p ui rms uip - p ui rms uip - p
a d n 2 8 0 9 r e v . p rb oc t . .20 0 1 - 3 - adn2809 electrical characteristics at t a =t min to t max , v cc =v min to v max , v ee =0v, c f =4.7 m f, 20 ohm esr for xo unless otherwise noted parameter conditions min typ max units jitter peaking maximum oc- 48 gigabit ethernet oc- 12 oc- 3 0.1 0.1 0.1 0.1 db db db db cml output format single - ended output voltage swing v se differential outpu t voltage swing v diff rise time (t r ) fall time (t f ) output high voltage v oh output low voltage v ol data setup time t s (figure 1) data hold time t h (figure 1) see figure 2 and figure 6 see figure 2 and figure 6 20% - 80% 80% - 20% figure 6 figure 6 oc48 gigabit ethernet oc12 oc3 oc48 gigabit ethernet oc12 oc3 300 600 vcc -0.55 150 350 750 3150 150 350 750 3150 430 860 vcc 550 1100 150 150 vcc -0.32 mv mv ps ps v v ps ps ps ps ps ps ps ps test data dc characteristics input voltage swing v se (figure 2) input voltage range single - ended single - ended 0.06 2.3 0.8 vcc+0.4 v v lvttl dc characteristics v oh output high voltage v ol output low volta ge v ih input high voltage v il input low voltage i ih input high current i il input low current i oh = - 100ua (adn2809 sources i) i ol = 1.0ma (adn2809 sinks i) vin = +2.4 v @ +25c vin = +0.5 v @ +25c 2.4 2.0 - 500 0.5 0.8 50 v v v v m a m a refclk dc characteristics input voltage swing v se (figure 2) input voltage range single - ended single - ended 0.032 0 vcc vcc v v note: (1) recommended for optimum sensitivity. note: (2) equipment limitation. a bsolute maximum ratings supply voltage....................................... ....................... ...+8 v input voltage (pin x or pin xto vcc).... ........................... .tbd maximum junction temperature............ ................. .165 deg c storage temperature range...... ........ - 65 deg c to +150 deg c lead temperature (soldering 10 sec).. ................ ....300 deg c esd rating (human body model)....... ........................... ..tbd stress above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at th ese or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. ordering guide model temp range package descript -ion option adn2809xcp - 40/+85 o c lfcsp - 16 cp - 16 adn2809xcp - rl - 40/+85 o c lfcsp - 16 2500 pieces cp - 16
a d n 2 8 0 9 r e v . p r b oc t . .20 0 1 - 4 - f i g u r e 1 . o u tput t im i ng d e f i n itio ns f i gur e 3. q u a nti z er s i gna l d ef i nit i ons f i g u r e 2 . s i g n a l l e v e l de f i n i t i o n f i gu r e 4. l o s c om pa r a t or t r i p p oi nt p r og r a m m i ng oc-48 2^23 los curve 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 0 20000 40000 60000 80000 100000 120000 140000 160000 180000 200000 rthresh los trip voltage (mv)
a d n 2 8 0 9 r e v . p r b oc t . .20 0 1 - 5 - figure 5: adn2809 jitter filtering & tracking bandwidth oc3_jit_tolerance oc12_jit_tolerance gbe_jit_tolerance oc48_jit_tolerance oc3_jit_transfer oc12_jit_transfer gbe_jit_transfer oc48_jit_transfer -10 -9.5 -9 -8.5 -8 -7.5 -7 -6.5 -6 -5.5 -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -.5 0 1e3 1e4 1e5 1e6 1e7 1e8 freq, hertz f i gur e 5. t r a c k i ng b a ndw i dt h a nd j i t t e r f i l t e r i ng jitter transfer jitter tolerance rate sonet spec adn2809 margin sonet spec adn2809 margin oc48 2mhz 370khz 5.4 1mhz 4.77mhz 4.8 gbe 1mhz 185khz 5.4 500khz 4.77mhz 9.6 oc12 500khz 93khz 5.4 250khz 4.77mhz 19.2 oc3 130khz 23khz 5.6 65khz 4.77mhz 73.4 db t a bl e i. t y pi c a l j i t t e r t r a ns f e r a nd j i t t e r t ol e r a nc e p e r f or m a nc e
a d n 2 8 0 9 r e v . p r b oc t . .20 0 1 - 6 - f ig u r e 6 . r ec o m m en d ed a c ou tp u t t er m in a tio n f ig u r e 7 . a dn 2 8 09 s 1 1 v s. f r eq u en cy
a d n 2 8 0 9 r e v . p r b oc t . .20 0 1 - 7 - theory of operation the adn2809 is a delay - and phase - locked loop circuit for clock recovery a nd data retiming from an nrz encoded data stream. the phase of the input data signal is tracked by two separate feedback loops which share a common control voltage. a high speed delay - locked loop path uses a voltage controlled phase shifter to track the h igh frequency components of input jitter. a separate phase control loop, comprised of the vco, tracks the low frequency components of input jitter. the initial frequency of the vco is set by yet a third loop which compares the vco frequency with the reference f requency and sets the coarse tuning voltage. the jitter tracking phase - locked loop controls the vco by the fine tuning control. the delay - and phase - loops together track the phase of the input data signal. for example, when the clock lags input data, the phase detector drives the vco to higher frequency, and also, increases the delay through the phase shifter: these actions both serve to reduce the phase error between the clock and data. the faster clock picks up phase while the delayed data loses phase. since the loop filter is an integrator, the static phase error will be driven to zero. another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second order phase - locked loop, and this zero is placed in the feedback path and thus, does not appear in the closed - loop transfer function. jitter peaking in a conventional second order phase - locked loop is caused by the presence of this zero in the closed -loop transfer function. since this circuit has no zero in the closed -loop transfer, jitter peaking is minimized. the delay - and phase - loops together simultaneously provide wide - band jitter accommodation and narrow - band jitter filtering. the linearized block diagram in figure 8 shows the jitter transfe r function , z(s)/x(s), is a second order low pass providing excellent filtering. note the jitter transfer has no zero, unlike an ordinary second order phase - locked loop. this means that the main pll loop has low jitter peaking, see figure 9. this makes th is circuit ideal for signal regenerator applications where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation. the error transfer, e(s)/x(s), has the same high pass form as an ordinary phase - locked loop. this tran sfer function is free to be optimized to give excellent wide - band jitter accommodation since the jitter transfer function, z(s)/x(s), provides the narrow - band jitter filtering. see figure 5 for a table of error transfer bandwidths and jitter transfer bandw idths at the various data rates. the delay - and phase - loops contribute to overall jitter accommodation. at low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with smal l phase error. in this case the vco is frequency modulated and jitter is tracked as in an ordinary phase - locked loop. the amount of low frequency jitter that can be tracked is a function of the vco tuning range. a wider tuning range gives larger accommodat ion of low frequency jitter. the internal loop control voltage remains small for small phase errors, so the phase shifter remains close to the center of its range and thus contributes little to the low frequency jitter accommodation. at medium jitter frequencies, the gain and tuning range of the vco are not large enough to track input jitter. in this case the vco control voltage becomes large and saturates and the vco frequency dwells at one or the other extreme of its tuning range. the size of the vco tun ing range, therefore has only a small effect on the jitter accommodation. the delay - locked loop control voltage is now larger, and so the phase shifter takes on the burden of tracking the input jitter. the phase shifter range, in ui, can be seen as a broad plateau on the jitter tolerance curve . the phase shifter has a minimum range of 2ui at all data rates. the gain of the loop integrator is small for high jitter frequencies, so that larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. large phase errors at high jitter frequencies cannot be tolerated. in this region the gain of the integrator determines the jitter accommodation. since the gain of the loop integrator declines linearly with f requency, jitter accommodation is lower with higher jitter frequency. at the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. in this case, jitter accommodation is determined by the eye opening of th e input data, the static phase error, and the residual loop jitter generation. the jitter accommodation is roughly 0.5ui in this region. the corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay - locked l oop, which is roughly 3mhz for all data rates.
a d n 2 8 0 9 r e v . p r b oc t . .20 0 1 - 8 - f ig u r e 8 . a dn 2 8 0 9 a r ch itect u r e f ig u r e 9 . a dn 2 8 0 9 j itter r esp o n se v s. con v en tiona l p l l adn2809
a d n 2 8 0 9 r e v . p r b oc t . .20 0 1 - 9 - functional description limiting amplifier / bypass & loopback the limiting amplifier has differential inputs (pin/nin), which are normally ac coupled to the internal 50 ohm terminati on (although dc coupling is possible). input offset is factory trimmed to achieve better than 6mv typical sensitivity with minimal drift. the quantizer slicing level can be offset by +/ - 100mv to mitigate the effect of ase (amplified spontaneous emission) noise by a differential voltage input of +/ - 0.8v applied to ?slicep/n? inputs. if no adjustment of the slice level is needed, slicep/n should be tied to vcc. when the ?bypass? input is driven to a ttl high state, the quantizer output is connected directly to the buffers driving the data out pins, thus bypassing the clock recovery circuit (figure 10). this feature can help the system to deal with non standard bit rates. the loopback mode can be invoked by driving the ?loopen? pin to a ttl high state, which facilitates system diagnostic testing. this will connect the test inputs (tdinp/n) to the clock and data recovery circuit (per figure 10). the test inputs can be left floating, when not in use. they accept ac or dc coupled signal levels, or ac coupled lvd s. loss of signal (los) detector the receiver front end signal detect circuit indicates when the input signal level has fallen below a user adjustable threshold. the threshold is set with a single external resistor, as illustrated in figure 4, which assu mes that the slice inputs are inactive. if the los detector is used the quantizer slice adjust pins must both be tied to vcc, to avoid interaction with the los threshold level. note that it is not expected to use both los and slice adjust at the same tim e: systems with optical amplifiers need the slice adjust to evade ase, but a loss of signal causes the optical amplifier output to be full scale noise, thus the los would not detect the failure. in this case the loss of lock signal will indicate the failur e. reference clock the adn2809 can accept any of the following reference clock frequencies: 19.44 mhz, 38.88mhz, 77.76mhz at lvttl/lvcmos/lvpecl/lvds levels or 155.52mhz at lvpecl/lvds levels via the refclkn/p inputs, independent of data rate (including gigabit ethernet). the input buffer accepts any differential signal with a peak to peak differential amplitude of greater than 64mv (e.g. lvpecl or lvds) or a standard single ended low voltage ttl input, providing maximum system flexibility. the appropria te division ratio can be selected using the refsel0/1 pins, according to table 3. phase noise and duty cycle of the reference clock are not critical and 100ppm accuracy is sufficient. a crystal oscillator is also provided, as an alternative to using the r efclkn/p input. details of the recommended crystal are given in table 3. refsel must be tied to vcc when the refclkn/p inputs are active, or tied to vee when the oscillator is used. no connection between the xo pin and refclk input is necessary (see figure 11). please note that the crystal should operate in series resonant mode, which renders it insensitive to external parasitics. no trimming capacitors are required. lock detector operation the lock detector monitors the frequency difference between the vco and the reference clock, and de - asserts the ?loss of lock? signal when the vco is within 500ppm of center frequency. this enables the phase loop which then maintains phase lock, unless the frequency error exceeds 0.1%. should this occur, the ?loss of l ock? signal is re - asserted and control returns to the frequency loop which will re - acquire, and maintain a stable clock signal at the output. the frequency loop requires a single external capacitor between cf1 and cf2. the capacitor specification is give n in table 5. squelch mode when the ?squelch? input is driven to a ttl high state, both the clock and data outputs are set to the zero state, to suppress downstream processing. if desired, this pin can be directly driven by the los (loss - of - signal) or lo l (loss - of - lock) detector outputs. if the squelch function is not required, the pin should be tied to vee.
a d n 2 8 0 9 r e v . p r b oc t . .20 0 1 - 10 - f igur e 11 . r ef er ence s o ur ces f i g u r e 1 2 . d a t a i nput t er m i na t i ons note: the value of cin required depends on the data rate, # consecutive identical digits (cid) and amount of patter dependent jitter (pdj) which can be tolerated. e.g. for 1000 cid and <0.01ui pk - pk pdj, 100nf is needed at oc48 and 1.6uf at oc3. adn 2809 adn 2809 f igu r e 10 . t es t m od es
a d n 2 8 0 9 r e v . p r b oc t . .20 0 1 - 11 - table 2. data rate selection sel2 sel0 sel1 rate frequency 0 0 0 oc48 2.48832 ghz 0 0 1 gigabit ethernet 1.25 ghz 0 1 0 oc12 622.08 mhz 0 1 1 oc3 155.52 mhz 1 0 0 oc48 * 15/14 2.666 ghz 1 0 1 gigabit ethernet * 15/14 1.339 ghz 1 1 0 oc12 * 15/14 666.51 mhz 1 1 1 oc3 * 15/14 166.63 mhz table 3. reference frequency selection refsel1 refsel0 applied reference frequ ency 0 0 19.44 mhz 0 1 38.88 mhz 1 0 77.76 mhz 1 1 155.52 mhz table 4. crystal specification - see note ( 3) parameter value mode series resonant frequency / overall stability 19.44 mhz / +/ - 50 ppm frequency accuracy temp. stab ility ageing +/ - 50 ppm / total temp. stability esr 20 ohms max (3 ) no additional external components are required table 5. recommended capacitor specif ication parameter value capacitance (- 40c to 85c) >3.0uf leakage (- 40c to 85c) <80na rating >6.3v
a d n 2 8 0 9 r e v . p r b oc t . .20 0 1 - 12 - adn2809 pin description pin no. name i/o level description 2,26,28, exposed pad vcc p 3.3v analog power 3,9,27,29, 42 vee g 0v analog ground 20,35,36,47 vcc p 3.3v digital supply 1 thradj i/o analog i/o los threshold setting resistor 4 vregf i/o analog i/o reference capacitor 5 pin i analog current differential data signal input 6 nin i analog current differential data signal input 7 slic ep i analog voltage slice level 8 slicen i analog voltage slice level 10 lol o lvttl / lvcmos high level indicates loss of lock 11 xo o analog output crystal oscillator 12 xo o analog output crystal oscillator 13 refclkn i any differential reference clock 14 refclkp i any differential reference clock 15 refsel i lvttl / lvcmos reference source select 17 tdinp i cml differential test data input 18 tdinn i cml differential test data input 21 cf1 i/o analog i/o frequency loop capacitor 23 refsel1 i lvttl / lvcmos reference rate select 24 refsel0 i lvttl / lvcmos reference rate select 25 cf2 i/o analog i/o frequency loop capacitor 30 sel2 i lvttl / lvcmos data rate select 31 sel1 i lvttl / lvcmos data rate select 32 sel0 i lvttl / lvcmos data rate select 37 dataoutn o cml differential recovered data 38 dataoutp o cml differential recovered data 39 squelch i lvttl / lvcmos disable clock and data outputs 40 clkoutn o cml differential retimed clock 41 clkoutp o cml differential retimed clock 44 bypass i lvttl / lvcmos disable clock and data recovery 45 sdout o lvttl / lvcmos high level indicates loss of signal 48 loopen i lvttl / lvcmos enable high speed test data inputs adn2809 pin configuration
a d n 2 8 0 9 r e v . p r b oc t . .20 0 1 - 13 - mechanical outline dimensions dimensions shown in millimeters and (inches).

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